1. Technical Field
The present invention relates to a method for manufacturing a printed circuit board.
2. Description of the Related Art
Since a semiconductor package substrate has high integration and high speed by degrees and a connecting type thereof with semiconductor is developing from the existing wire bonding type to a flip chip bonding type, a demand that different kinds of surface treatments are applied to a single printed circuit board is increasing.
In a method for manufacturing a printed circuit board according to the prior art, a process for application of different kinds of surface treatments is as follows.
First, an outer layer circuit is formed on an upper surface of a substrate having an inner layer circuit.
Here, the outer layer circuit may include wire bonding pads for connecting a semiconductor chip or the like to the substrate by using wires of gold (Au), silver (Ag), copper (Cu), or the like, bump pads for connecting another semiconductor chip or the like to the substrate by using solder bumps or the like, that is, for flip-chip connection, and circuit patterns.
The outer layer circuit may be generally formed in the following process sequence.
First, an insulating layer is formed on the upper surface of the substrate having the inner layer circuit, and a via hole is formed in the insulating layer. The result substrate is subjected to electroless plating, thereby forming a seed layer.
Next, a plating resist is formed on the insulating layer on which the seed layer is formed, and then, a patterned mask is disposed above an upper surface of the plating resist. Then, an opening for forming the outer layer circuit is formed in the plating resist by carrying out exposing and developing processes, and a plating layer is formed by carrying out electroplating.
After the outer layer circuit is formed through the above-described processes, a plating resist having an opening for exposing the wired bonding pads is formed on the insulating layer on which the outer layer circuit is formed. A first surface treatment layer is formed by performing electroplating on the wire bonding pads, and then the plating resist is removed.
A solder resist layer having openings for respectively exposing the wire bonding pads and the bump pads is formed, and then a second surface treatment layer is formed on the bump pads by using an organic solderability preservative OSP type.
However, this method according to the prior art includes two processes of forming and removing the plating resist for forming the outer layer circuit and the first surface treatment layer and a process of forming a solder resist layer, and thus, the number of processes is increased and the processing time is longer, thereby lowering the processing efficiency.